Magnetic core circuits for binary coded information



Aug. 16. 1966 A. M. RICHARD MAGNETIC CORE CIRCUITS FOR BINARY CODEDINFORMATION Original Filed July 15, 1957 FiGA V' e 3,2h7A44 lc PatentedAugust 16, 1965 3,267,444 MAGNETIC CORE CIRCUITS FOR BINARY CODEDINFDRMATIGN Andre Michael Richard, Paris, France, assigner to SocietedElectroniqne et dAutomatisme, Courbevoie, France Original applicationJuly 15, 1957, Ser. No. 671,854, now Patent No. 3,058,098, dated Oct. 9,1962. Divided and this application Sept. 13, 1962, Ser. No. 223,445Claims priority, application France, July 21, 1956, 719,080, Patent1,156,488 5 Claims. (Cl. 340-174) This application is a division ofco-pending application Serial No. 671,854, now Patent No. 3,058,098, ledjointly by me and others -on July 15, 1957. The present application isconcerned with the subject matter of FIG- URES 1 to 3 of the earlierapplication.

The present invention is concerned with improvements in or relating tomagnetic core circuits for handling binary coded informations throughtemporary registrations of the digits thereof on the said cores andrepeatedly controlled progressions of these registrations -along atleast one cascade arrangement of the said cores in the said circuits.Usu-ally, each core is made of a material which presents a substantiallyrectangular hysteresis cycle so that two stable conditions of reversestates of magnetization may be obtained and m-ay serve for therepresentation of the binary digital values 0 and 1, according to apredetermined correspondence established between `the said two states ofmagnetization and the said two digital values. As will be apparent lateron, Ythe said correspondence may vary according to ra known lawthroughout the said cascade arrangement of magnetic cores. Each core isprovided with at least one write-in winding and one read-out winding andinterconnecting networks are provided between write-in windings andread-out windings of the cores for obtaining the said cascadearrangement along which a progression of a binary code may be suitablycontrolled. Each write-in winding of a core may receive a write-incurrent which, when of a special character with respect to the previousstate of magnetization of the concerned core, may change this strate ofmagnetization. Each read-out winding may carry a current which is of acharacter representative of the state of magnetization previouslyacquired by the concerned core.

The present invention is mainly concerned with an improved arrangementof interconnecting networks in a magnetic core circuit of theabove-specified kind for a more simple and eicient control of thehandling of binary coded informations therewith.

According to a feature of the invention, in a magnetic core circuit ofthe above-specified kind, each interconnecting network is active andcomprises a pair of terminals for the application thereto of atwo-polarity waveform control voltage, at least one read-out winding ofa magnetic core with one end thereof connected to one of the saidterminals, at least one write-in winding of a further magnetic core withone end thereof connected t-o the other one of the said terminals, thenumber of turns of the said write-in Winding being lower than the numberof turns of the said read-out winding, and a unidirectionally conductingelement completing a serial connection between the said two windings andthe said pair of terminals, all the unidirectionally conducting elementsbeing of the same direction of insertion in the said interconnectingnetworks but the said control voltages being of regularly opposed phasesin the application thereof to the successive interconnecting networks ofthe said magnetic core circuit.

The invention will now be detailed with reference to the accompanyingdrawings, wherein:

FIG. l shows an illustrative embodiment of a magnetic core circuitaccording to the invention;

FIG. 2 shows the magnetic characteristic of the cores of FIG. 1 undercertain conditions, yand FIG. 3 shows the wave form and phase relationsbetween the four control voltages of FIG. 1.

FIG. 1 shows a `part of a cascade arrangement comprising live magneticcores, I to V, each one of which is made of a material having asubstantially rectangular hysteresis cycle. Each core is provided, inthis embodiment, with three windings viz a write-in winding 6, aread-out winding 5 and a special winding 7. The writein or input winding6 is lfor instance of n2 turns and the read-out or output winding 5 ofn1 turns, with n2 lower than nl. The winding 7 will be used as aresetting winding though it will be later disclosed how and in whatconditions such a control winding may be dispensed with.

The digital value 1 will be represented by a definite condition A1 of amagnetic core whereas the digital value 0 will be represented by the`reverse condition A0. With respect to the embodiment of FIG. 1, it willbe assumed that the condition A1 will be the positive remanent inductionstate P of a core, and the condition A0 consequently the negativeremanent induction state N of a core, though of course the reverse maybe considered as well.

Each read-out winding 5 of a magnetic core: is serially connected withthe write-in winding 6 of the next following core in the sequence andthis serial connection includes a unidirectionally conducting element 8and a voltage source, The point of insertion `of the element 8 in thesaid serial connection may be at any desired location.

The voltage terminals of the networks interconnecting the cores I-II andIII-IV are branched off leads from circuit 1 supplying a rsttwo-polarity waveform voltage, and the voltage terminals of the networksinterconnecting the cores II-III and IV-V are branched off leads fromcircuit 3, supplying a second two-polarity waveform voltage.

The control windings 7 of alternate cores, such as the core-s II and IV,are serially connected in a current circuit 4, and the windings '7 ofthe remaining cores III and V are serially connected in a currentcircuit 2. Of course, the winding 7 of the rst core I is in the currentcircuit 2, though it is not shown.

The voltage land current waveforms supplied by circuits 1 to 4 may besuch as shown in FIG. 3, references 1 to 4. In any case, they are of twopolarity and may be pure A.C. waveforms as indicated in dot lines. Linesmarked 0 define the threshold level of action of the said waveforms intheir positive actions upon the cores. It is more apparent whenconsidering pure A.C. waveforms that 1 and 3 are in relative phaseopposition therebetween and that 2 and 4 are in phase opposit-iontherebetween, though a phaseshift of exists between the pair 1, 3 andthe pair 2, 4. The said currents and voltages act in four distinctsub-periods t1, t2, t3 and t4, constituting together the recurrenceperiod T of operation of the device.

For explaining the operation of the arrangement of FIG. 1, it will beassumed that it starts from a time instant when cores l and III recordthe digit-al value 1 and cores II, IV and V, the digital value 0. CoresI and III are in their P magnetic condition, cores II, IV and V in theirN condition.

On each core, windings 6 and 7 `are wound in opposite directions; seethe polarity dots in FIG. 1.

Core II has just been reset to its N condition by the positivealternation of current waveform 4 of FIG. 3 on the extreme left-handside. The same alternation had no effect on core IV since, as core V isin the N condition, core IV has previously remained in the said Nmagnetic condition.

Starting with the sub-period t1 of FIG. 3, the voltage applied cross Iand consequently across the terminals of interconnecting networksbetween cores I-II, and cores III-IV, finds a substantially negligibleimpedance path offered to the development of transfer electrical currentin each one of the windings 5 of cores I and III because the positivealternation of voltage 1 during t1 magnetizes these `cores beyond theirP remanant condition to an oversaturated magnetic condition. Such aphenomenon of negligible impedance is quite known per se.

The value of the current, established in a direction such that it istransmitted through diodes 8 in these interconnecting circuits, is thensolely determined by the impedance of the windings 6 of the receivercores therein. This current value is, for instance, z'c/nz, with z'c thesingleturn coercive current of any core and n2, as said, the number ofturns of any winding 6. It then actuates cores II and IV for changingtheir magnetic condition yfrom N to P during this time interval t1. Atthe end of such interval, all cores I to IV, inclusively, are in their Pcondition.

The cycle covered by the magnetic change of flux during t1 in cores IIand IV is shown in the right-hand part of FIG. 2.

As soon as a current starts to pass through the windings 5 of cores Iand III a magnetization effect tends to develop in these cores, but thiseffect is opposed by the action of the current 4 in the windings 7thereof, and further this effect would have been only that of a smallercurrent, z'c/ n1, where the numbe-r of turn nl of a winding 5 being, assaid, several times greater than 112. The security of operation is thusensured.

Then occurs a period t2 during which the current through the windings 7of cores I `and III, as shown at 2 in FIG. 3, acts for resetting boththe cores I and III to their N magnetic condition. The unidirectionallyconducting elements or diodes 8 which passed the first currents for thetransfer of magnetic conditions from I to II and from III to IV do notpass the current induced by the resetting of cores I and III in theirwindings 5. At the end of t2, cores I and III are in their N condition,cores II and IV are in their P condition. The registration hasprogressed by one step along the circuit.

During the third sub-period t3 it is the interconnecting networksbetween cores II-III `and cores IV-V which receive a suitablealternation from the supply leads 3, see FIG. 3, for enabling thepassage of current through the diodes S of their interconnectingnetworks Af-or the actuation of cores III and V from their N to their Pconditions. The transfer is effected lunder the same conditions as forthe transfer during t1, Ibut with a shift ot cores. Consequently, at theend of sub-period t3, cores II, III, IV and V are all in their Pcondition.

During t3, core I may have received or not an information bit of valuel. Suppose it has not, so this core I has remained in its N condition.

During t4, cores I and IV are -reset to their N condition as was thecase for I `and III during t2. Within each overall period T, obviously,each digit of the information has lprogressed by an effective step, thedigit standing on core I at the beginning standing now on core III `andthe digit vstanding on core III `at the beginning standing now on coreV, the registration of each one of the digits obviously needing a pairof cores for correct representation and progression.

In a new period T, the first sub-period t1 will bring core IV to the Pcondition and during sub-period t2, core III will be reset to N. Duringtl core 1I willremain at the N 75 condition as the current induced bythe positive alternation of the voltage 1 in the windings 5 and 6 in theinterconnecting circuit Ibetween I and II will lbe limited to a lowervalue since the impedance of 5 is not then negligible as this currenttends to desaturate the core I and so forth.

During the resetting periods, the current is ic/nl las shown in theleft-hand part of FIG. 2.

I claim:

1. A device for handling binary coded information cornprising at leastone -cascaded arrangement of magnetizable cores, each having asubstantially rectangular hysteresis cycle of magnetization and havingat least Vone write-in winding, and at least one read-out windingthereon, the write-in winding having a smaller number of turns than theread-out winding, said write-in and read-out windings on the said coresbeing wound to provide opposite directions of magnetization thereon, anda reset winding, a series network interconnecting each pair of adjacentcores and comprising in series circuit connection a readout winding onone core, a unidirectional conducting device, a write-in winding of anadjacent core, -and a source of alternating voltage; means connectingalternate ones of said network to receive alternating voltages of thesame phase relation and the remaining networks to receive alternatingvoltages of opposite phase with respect to the voltages supplied to saidalternate networks, and the unidirectionally conducting devices beingsimilarly connected to conduct current in the same direction in allnetworks and through bot-h windings of each network; and a source ofresetting current supplying said reset windings in any interval betweenthe active periods of write-in and readout alternations of the saidalternating voltage.

2. A device according to claim 1 wherein said reset winding on each corehas a sufficient number of ampereturns for -inhibiting a resetting ofthe core by the read-out winding, said reset winding operating to resetthe core due to a reversal of current therein between active write-inand read-out periods for the said cores.

3. A device for handling binary coded information comprising at leastone cascaded arrangement of magnetizable cores, each core having asubstantially rectangular hysteresis cycle of magnetization and 'havingat least one write-in winding, and at least one read-out'windingthereon, the write-in winding having a smaller number of turns than theread-out winding, and a reset winding, a series network interconnectingeach pair of adjacent cores and `comprising `in series circuitconnection a read-out winding on one core, a unidirectional conductingdevice, a writein winding of an `adjacent core, and a source ofalternating Voltage; means connecting alternate ones of said network toreceive alternating voltages of the same phase relation and theremaining networks to receive alternating voltages of opposite phasewith respect to the voltages supplied to said alternate networks, andthe unidirectionally conducting devices being similarly connected toconduct current in the same direction in all networks and through bothwindings of each network; and a source of resetting current supplyingsaid reset winding -in any interval beteen the active periods ofwrite-in and read-out alternations of the said alternating voltage.

4. A device according to claim 3 wherein the said reset winding on eachcore has a sufficient number of ampereturns for -inhibiting a resettingof the core by the read-out winding, and the said source of resettingcurrent operating to ensure said inhibiting action during the read-outperiods and to effect said resetting between active write-in andread-out periods for the said cores.

5. A device according to claim 3 wherein said source of `alternatingvoltage and said source of resetting current are of identicalfrequencies and in quadrature phase relation.

No references cited.

BERNARD KONICK, Primary Examiner. M. GITTES, Assistant Examiner.

1. A DEVICE FOR HANDLING BINARY CODED INFORMATION COMPRISING AT LEASTONE CASCADED ARRANGEMENT OF MAGNETIZABLE CORES, EACH HAVING ASUBSTANTIALLY RECTANGULAR HYSTERESIS CYCLE OF MAGNETIZATION AND HAVINGAT LEAST ONE WRITE-IN WINDING, AND AT LEAST READ-OUT WINDING THEREON,THE WRITE-IN WINDING HAVING A SMALLER NUMBER OF TURNS THAN THE READ-OUTWINDING, SAID WRITE-IN AND READ-OUT WINDINGS ON THE SAID CORES BEINGWOUND TO PROVIDE OPPOSITE DIRECTIONS OF MAGNETIZATION THEREON, AND ARESET WINDING, A SERIES OF NETWORK INTERCONNECTING EACH PAIR OF ADJACENTCORES AND COMPRISING IN SERIES CIRCUIT CONNECTION A READOUT WINDING ONONE CORE, A UNIDIRECTIONAL CONDUCTING DEVICE, A WRITE-IN WINDING OF ANADJACENT CORE, AND A SOURCE OF ALTERNATING VOLTAGE; MEANS CONNECTINGALTERNATE ONES OF SAID NETWORK TO RECEIVE ALTERNATING VOLTAGES OF THESAME PHASE RELATION AND THE REMAINING NETWORKS TO RECEIVE ALTERNATINGVOLTAGES OF OPPOSITE PHASE WITH RESPECT TO THE VOLTAGES SUPPLIED TO SAIDALTERNATE NETWORKS, AND THE UNIDIRECTIONALLY CONDUCTING DEVICES BEINGSIMILARLY CONNECTED TO CONDUCT CURRENT IN THE SAME DIRECTION IN ALLNETWORKS AND THROUGH BOTH WINDINGS OF EACH NETWORK; AND A SOURCE OFRESETTING CURRENT SUPPLYING SAID RESET WINDINGS IN ANY INTERVAL BETWEENTHE ACTIVE PERIODS OF WRITE-IN AND READOUT ALTERNATIONS OF THE SAIDALTERNATING VOLTAGE.